Since their emergence in the second half of the twentieth century, the information processing systems have ceaselessly increased in complexity to execute increasingly computation-intensive tasks. In the past, a conventional approach for improving the capacities of the processors of the information processing systems has been to increase the operating frequency of these processors and miniaturize them more. However, this approach has shown its limitations because it was inducing strong energy consumption increases and increased processor cooling needs. A new approach then became popular and consisted in creating processors comprising multiple computation cores (hereinafter simply called cores). Two types of processors comprising multiple cores are distinguished: the so-called many core (or “manycore”) processors and the multiple core processors. The many core processors differ from the multicore processors in the number of cores in one and the same processor. Thus, an order of magnitude of the number of cores in a multicore processor is ten or so cores whereas a many core processor can contain a hundred or even a thousand or so cores. The many core and multicore processors thus have different architectures, suited to the number of cores.
In general, the many core processors are organized in computation groups (or clusters) grouping together several cores sharing resources local to the computation group. The computation groups of a many core processor can communicate with one another and with resources external to the computation group by using a network internal to the processor called network on chip (NoC). A network on chip can for example be a meshed network.
Some many core processor topologies comprise two types of computation groups: the application computation groups dedicated to executing applications and the input/output computation groups dedicated to communications with resources external to the processor.
It is common practice in many core processors for each computation group to have a memory shared between the cores of the computation group. These shared memories generally have small sizes compared to the information processing code sizes and to the data that the many core processors have to manipulate. An implementation of an information processing program, implementing an application, then requires a use of a memory external to the processor. This external memory then becomes a memory shared between different applications implemented by the processor. Interferences can then appear between these different applications during writes or reads in the external memory.
It is desirable to mitigate this drawback in the prior art. It is in particular desirable to propose a mechanism which allows applications running on a many core processor to access the remote memory while guaranteeing non-interference between the different applications.